1. Field of the Invention
The present invention relates to an electric power semiconductor apparatus (referred to as a power semiconductor apparatus hereinafter) including a plurality of electric power controlling semiconductor modules (referred to as power controlling semiconductor modules hereinafter) connected in parallel to each other, and in particular, to a power semiconductor apparatus including a plurality of electric power controlling semiconductor modules such as intelligent power modules (referred to as IPMs hereinafter) connected in parallel to each other for controlling driving of power semiconductor devices such as metal oxide semiconductor field effect transistors (referred to as MOSFETs hereinafter) or insulated gate bipolar transistors (referred to as IGBTs hereinafter).
2. Description of the Related Art
Prior arts in relation to the power semiconductor apparatus including a plurality of electric power controlling semiconductor modules such as IPMs connected in parallel to each other for controlling driving of power semiconductor devices such as MOSFETs or IGBTs are disclosed in the following prior art documents.
(1) Japanese patent laid-open publication No. 2002-369497 (referred to as a first prior art document hereinafter).
(2) International patent laid-open publication No. WO01/089090 (referred to as a second prior art document hereinafter).
(3) Japanese patent laid-open publication No. 10-042548 (referred to as a third prior art document hereinafter).
(4) Japanese patent laid-open publication No. 10-014215 (referred to as a fourth prior art document hereinafter).
(5) Japanese patent laid-open publication No. 2002-369496 (referred to as a fifth prior art document hereinafter).
(6) Japanese patent laid-open publication No. 08-213890 (referred to as a sixth prior art document hereinafter).
(7) Japanese patent laid-open publication No. 2000-092820 (referred to as a seventh prior art document hereinafter).
The first prior art document discloses the following solving means for trying to prevent misdetection of overcurrent and heat concentration caused by switching over unbalance among power devices, when IPMs, each of which is made to be intelligent by providing a gate driving circuit in each of the power devices, operate under such a condition that they are connected in parallel to each other. FIG. 1 of the first prior art document shows the following invention. When two IPM circuits 2A and 2B, for example, operate in such a condition that they are connected in parallel to each other, output signals from delay circuits D1A and D2A that delay an operation command signal L1 are transmitted to the IPM circuit 2B, and output signals from delay circuits D1B and D2B are transmitted to the IPM circuit 2A so as to prevent switching over unbalance between power devices 3A and 3B of the respective IPM circuits 2A and 2B.
In addition, the second prior art document discloses the following solving means for loosening a criteria of selecting switching devices that constitute IPMs based on switching characteristics thereof, and for equally applying a current to the respective IPMs connected in parallel to each other. FIG. 1 of the second prior art document shows the following invention. First main electrodes, which are main current input-side electrodes of two switching devices, are connected to each other and second main electrodes, which are main current output-side electrodes of the two switching devices, are connected to each other. Such resistances that have a common resistance value are connected to the respective second main electrodes. A first wiring conductor connects the respective second main electrodes to each other via the resistances and auxiliary terminals thereof. A second wiring conductor connects control electrodes of the respective switching devices to each other via an impedance element having high impedance at a predetermined frequency.
Further, the third prior art document discloses the following solving means for preventing current distribution unbalance among semiconductor devices connected in parallel to each other and for realizing a semiconductor power converter apparatus having a desired capacity being small in size and inexpensive. FIG. 1 of the third prior art shows the following invention. In a semiconductor power converter apparatus including a plurality of power semiconductor devices connected in parallel to each other within one arm, anodes of IGBTQ1 and IGBTQ2 are connected to each other, control electrodes thereof are connected to each other, and cathodes thereof are connected to each other via inductance components L1 and L2, respectively. A gate driver circuit GDU is connected between a mutual connection point of the inductance components L1 and L2 and a mutual connection point of the control electrodes. Further, resistances are connected between each of the control electrodes and the GDU, respectively, and overvoltage protector circuits are connected between each of the control electrodes and each of the cathodes, respectively.
Still further, the fourth prior art document discloses the following solving means for performing a stable switching even if turn-on characteristics of switching devices operating in parallel are different from each other. FIG. 1 of the fourth prior art document shows the following invention. If one of switching devices 2 and 3 that are connected in parallel to each other is turned on faster than another, a current ΔiE flows in a circuit which connects emitter auxiliary terminals of the switching devices 2 and 3 to each other, due to an induced voltage generated by a floating inductance of a wiring on an emitter main circuit side of above-mentioned one of the switching devices 2 and 3. In addition, a voltage for dropping a gate voltage of the switching device is induced in a floating inductance of this circuit, however, the current ΔiE is reduced by an inductance of a transformer 12, and the voltage for dropping the gate voltage is suppressed. Then, such a phenomenon that the switching device is turned off while being turned on is prevented.
In addition, the fifth prior art document discloses the following solving means for trying to prevent misdetection of overcurrent and heat concentration caused by switching over unbalance among power devices, when IPMs, each of which is made to be intelligent by providing a gate driving circuit in each of the power devices, operate under such a condition that they are connected in parallel to each other. FIG. 1 of the fifth prior art document shows the following invention. When two IPM circuits 2A and 2B, for example, operate in such a condition that they are connected in parallel to each other, output signals from delay circuits D1A and D2A that delay an operation command signal L1 are transmitted to the IPM circuit 2B, and output signals from delay circuits D1B and D2B are transmitted to the IPM circuit 2A so as to prevent switching over unbalance between power devices 3A and 3B of the respective IPM circuits 2A and 2B.
Further, FIG. 1 of the sixth prior art document discloses the following solving means for trying to prevent misdetection of overcurrent and heat concentration caused by switching over unbalance among power devices, when IPMs, each of which is made to be intelligent by providing a gate driving circuit in each of power devices 3, operate under such a condition that they are connected in parallel to each other. FIG. 1 of the sixth prior art document shows the following invention. When the IPMs are used in such a state that they are connected in parallel to each other, the switching over unbalance between respective power devices 3 of circuits A and B is prevented by short-circuiting gates of the respective power devices 3 to each other through a short-circuit line 8.
Still further, the seventh prior art document discloses solving means for eliminating current unbalance among switching devices connected in parallel to each other with high accuracy. FIG. 12 of the seventh prior art document, the following steps are executed.
(1) Current sense voltages VCS1 to VCSn, which are detected values of main currents of “n” (where “n” is a positive integer of two or more.) IGBTs connected in parallel to each other are converted into digital voltages and then subjected to an arithmetic processing.
(2) The current sense voltages VCS1 to VCSn are converted into collector currents I1 to In using constants G1 to Gn and offset voltages VOFFSET1 to VOFFSETn, respectively (in step 103), and then deviations ΔI1 to ΔIn from an average IAVG of the collector currents I1 to In (in steps 104 and 105) are calculated.
(3) Driving control voltages VD1 to VDn are updated by as much as variations ΔVD1 to ΔVDn obtained by multiplying the deviations ΔI1 to ΔIn by coefficients Kij, respectively (in steps 106 and 107).
(4) The driving control voltages VD1 to VDn are converted into analog voltages, and the resultant analog voltages are supplied to the n IGBTs as gate voltages VGE, respectively. The constants G1 to Gn, the offset voltages VOFFSET1 to VOFFSETn, and the coefficients Kij are prepared for the “n” switching devices individually.
Above-mentioned prior arts mainly disclose concrete preventive means for preventing unbalance among currents that flow in respective IPMs or switching devices connected in parallel to each other, however, the prior arts have the following disadvantage. Generally speaking, protection circuits are connected to the respective IPMs or switching devices. A protection circuit provided in one of the IPMs or switching devices can operate so as to cut off an operation of this one of the IPMs or switching devices, on the other hand, another IPM or switching device continuously operates. By this operation, such a disadvantage that another IPM or switching device is destroyed or deteriorated, which results in decrease in lifetime thereof, arises.